HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 542

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
Note: In operation with an external clock source, be sure that t >4 states.
SCK
TDRE
When an external clock source is used for the serial clock, after the DMAC updates TDR,
allow an inversion of at least five system clock ( ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur (see figure 13.22) .
To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
D = 0.5, F = 0
M =
= 46.875%
Figure 13.22 Example of Synchronous Transmission Using DMAC
(0.5
t
D0
2
1
16
D1
)
100%
D2
D3
D4
Rev. 2.0, 06/04, page 513 of 980
D5
. . . . . . . . (2)
D6
D7

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