HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 192

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
6.5.9
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column
address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external
data bus are output. In the case of
connected.
Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the
selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and
corresponding output pin selections.
Read access
Write access
Byte Access Control and CAS
Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0)
(
(
Note: n = 2 to 5
PB
PB
4
4
D
D
A
/PB
/PB
/
/
23
15
15
(
(
(
to A
5
to D
5
to D
)
)
)
)
0
0
0
)
CAS
CAS
CAS Output Pin
16-bit organization DRAM, the 2-CAS type can be
T
p
Tr
Row
Trw
High level
High level
T
c1
Rev. 2.0, 06/04, page 163 of 980
Column
Tw
Write data
Tw
Read data
T
c2

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