HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 282

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 7.14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
7.6.8
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
7.6.9
When the A/D converter is set to scan mode and conversion is performed on more than one
channel, the A/D converter generates a transfer request when all conversions are completed. The
converted data is stored in the appropriate ADDR registers. Block transfer mode and full address
mode should therefore be used to transfer all the conversion results at one time.
Address bus
RD
HWR
,
LWR
Bus Cycle when Transfer is Aborted
Transfer Requests by A/D Converter
Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
CPU cycle
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
T
1
T
2
T
d
T
1
DMAC cycle
T
2
T
1
T
2
T
1
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
CPU cycle
DTE bit is
cleared
T
2
Rev. 2.0, 06/04, page 253 of 980
T
3
T
d
DMAC
cycle
T
d
T
1
CPU cycle
T
2