HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 231

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 7.4.
Table 7.4
Channel
0
1
7.2.1
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1.
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from
serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt,
and as a source address register otherwise.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
Rev. 2.0, 06/04, page 202 of 980
Bit
Initial value
Read/Write
Register Descriptions (1) (Short Address Mode)
Memory Address Registers (MAR)
31
—
Bit 2
DTS2A
1
Other than above
1
Other than above
30
—
Selection of Short and Full Address Modes
29
—
MARR
28
—
27
—
Bit 1
DTS1A
1
1
26
—
25
—
24
—
R/W
23
Description
DMAC channel 0 operates as one channel in full address mode
DMAC channels 0A and 0B operate as two independent channels
in short address mode
DMAC channel 1 operates as one channel in full address mode
DMAC channels 1A and 1B operate as two independent channels
in short address mode
R/W
22
R/W
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
R/W
17
Undetermined
R/W
16
R/W
15
R/W
14
R/W
13
R/W
MARH
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0