HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 80

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.8.2
In this state the CPU executes program instructions in normal sequence.
2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
Priority
High
Low
Exception
sources
Program Execution State
or immediately after reset exception handling.
Exception-Handling State
Type of Exception Detection Timing
Reset
Interrupt
Trap instruction
Reset
Interrupt
Trap instruction
Figure 2.12 Classification of Exception Sources
Synchronized with clock
End of instruction
execution or end of
exception handling*
When TRAPA instruction
is executed
External interrupts
Internal interrupts (from on-chip supporting modules)
Start of Exception Handling
Exception handling starts immediately
when
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed
4-5
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changes from low to high