HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 20

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2
7.3
7.4
7.5
7.6
Section 8 I/O Ports .............................................................................................255
8.1
8.2
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 202
7.2.1
7.2.2
7.2.3
7.2.4
Register Descriptions (2) (Full Address Mode) ................................................................ 208
7.3.1
7.3.2
7.3.3
7.3.4
Operation .......................................................................................................................... 217
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 244
7.4.11 NMI Interrupts and DMAC ................................................................................. 245
7.4.12 Aborting a DMAC Transfer................................................................................. 246
7.4.13 Exiting Full Address Mode.................................................................................. 247
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 248
Interrupts........................................................................................................................... 249
Usage Notes ...................................................................................................................... 250
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
Overview........................................................................................................................... 255
Port 1................................................................................................................................. 258
8.2.1
Register Configuration......................................................................................... 200
Memory Address Registers (MAR) ..................................................................... 202
I/O Address Registers (IOAR) ............................................................................. 203
Memory Address Registers (MAR) ..................................................................... 208
I/O Address Registers (IOAR) ............................................................................. 208
Overview.............................................................................................................. 217
I/O Mode.............................................................................................................. 219
Idle Mode............................................................................................................. 221
Repeat Mode ........................................................................................................ 224
Normal Mode....................................................................................................... 227
Block Transfer Mode ........................................................................................... 230
DMAC Activation................................................................................................ 235
DMAC Bus Cycle ................................................................................................ 237
Multiple-Channel Operation ................................................................................ 243
Note on Word Data Transfer................................................................................ 250
DMAC Self-Access.............................................................................................. 250
Note on Full Address Mode Setup....................................................................... 250
Memory and I/O Address Register Values .......................................................... 252
Bus Cycle when Transfer is Aborted ................................................................... 253
Transfer Requests by A/D Converter................................................................... 253
Overview.............................................................................................................. 258
Input/Output Pins................................................................................................. 200
Execute Transfer Count Registers (ETCR).......................................................... 203
Data Transfer Control Registers (DTCR) ............................................................ 205
Execute Transfer Count Registers (ETCR).......................................................... 209
Data Transfer Control Registers (DTCR) ............................................................ 211
Longword Access to Memory Address Registers ................................................ 250
Note on Activating DMAC by Internal Interrupts ............................................... 251
NMI Interrupts and Block Transfer Mode ........................................................... 252
Rev. 2.0, 06/04, page xv of xxiv