HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 248

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.2
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the
address specified in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6
Register
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 7.2 illustrates how I/O mode operates.
23
23
All 1s
Memory address register
15
I/O Mode
MAR
Register Functions in I/O Mode
ETCR
7
IOAR
0
0
0
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer counter
Function
Other
Activation
Source
address
register
Destination
address
register
Initial Setting
Destination or
source start
address
Source or
destination
address
Number of
transfers
Rev. 2.0, 06/04, page 219 of 980
Operation
Incremented or
decremented
once per
transfer
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends