HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 539

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4
The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error
interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table
13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or
disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the
interrupt controller.
A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested
when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer
data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request
cannot activate the DMAC.
An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the
DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An
ERI interrupt request cannot activate the DMAC.
The DMAC can be activated by interrupts from SCI channel 0.
Table 13.12 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
13.5
13.5.1
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Rev. 2.0, 06/04, page 510 of 980
SCI Interrupts
Usage Notes
Notes on Use of SCI
Description
Receive error (ORER, FER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
Priority
High
Low