HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 569

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The receive margin can therefore be expressed as follows.
Receive margin in smart card interface mode:
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.
When D = 0.5 and F = 0:
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as
described below.
1. If an error is found when the received parity bit is checked, the PER bit is automatically set to
2. The RDRF bit in SSR is not set for the frame in which the error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.
4. If no error is found when the received parity bit is checked, the receive operation is assumed to
5. When a normal frame is received, the data pin is held in the high-impedance state at the error
Rev. 2.0, 06/04, page 540 of 980
Retransmission when SCI is in Receive Mode
Figure 14.12 illustrates retransmission when the SCI is in receive mode.
1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit
should be cleared to 0 in SSR before the next parity bit sampling timing.
have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE
bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA
transfer activation source, the RDR contents can be read automatically. When the DMAC
reads the RDR data, the RDRF flag is automatically cleared to 0.
signal transmission timing.
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (L = 0 to 1.0)
L: Frame length (L =10)
F: Absolute deviation of clock frequency
M = (0.5 – 1/2
M = (0.5 –
= 49.866%
2N
1
372)
) – (L – 0.5) F –
100%
D – 0.5
N
(1 + F)
100%