HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 627

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Name of
Parameter
Table 18.6 Usable Parameters and Target Modes
Download
pass/fail result
Flash pass/fail
result
Flash
programming/
erasing
frequency
control
Flash user
branch address
set parameter
Flash
multipurpose
address area
Flash
multipurpose
data destination
area
Flash erase
block select
Note:
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the area as much as 4 kbytes starting from the start address specified by
FTDAR. For the address map of the on-chip RAM, see figure 18.10.
The download control is set by using the programming/erasing interface register. The return value
is given by the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the
start address of the on-chip RAM area specified by FTDAR to a value other than the return value
of download (for example, H'FF) before the download start (before setting the SCO bit to 1).
Refer to item 18.5.2 (e) for information on the method for checking the download result.
Rev. 2.0, 06/04, page 598 of 980
specified by FTDAR)
* One byte of start address of download destination specified by FTDAR
Abbrevia-
tion
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
Down-
load
—
—
—
—
—
—
Initiali-
zation
—
—
—
—
Program-
ming
—
—
—
—
Erasure
—
—
—
—
—
R/W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Alloca-
tion
On-
chip
RAM*
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER1 of
CPU
ER0 of
CPU
ER0 of
CPU