HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 158

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2.7
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time
select the RAS output pin corresponding to each DRAM space.
Bit 7
DRAS2
0
1
Note:
When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to
DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in
RTMCSR to clear the flag.
Bit
Read/Write
Initial value
* A single CSn pin serves as a common RAS output pin for a number of areas. Unused
Bit 6
DRAS1
0
1
0
1
DRAM Control Register A (DRCRA)
CSn pins can be used as input/output ports.
DRAS2
R/W
Bit 5
DRAS0 Area 5
0
1
0
1
0
1
0
1
7
0
DRAS1
Normal
Normal
Normal
Normal
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
R/W
6
0
5
4
2
)
)*
)*
DRAS0
R/W
5
0
Area 4
Normal
Normal
Normal
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
4
4
4
2
—
)
)
)*
)*
—
4
1
Description
R/W
BE
3
0
Area 3
Normal
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
Rev. 2.0, 06/04, page 129 of 980
3
2
3
3
2
2
)
)*
)
)
)*
)*
RDM
R/W
2
0
SRFMD
R/W
1
0
Area 2
Normal
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
2
2
2
2
2
2
2
)
)
)*
)
)
)*
)*
RFSHE
R/W
0
0