HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 324

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

standby mode it retains its previous setting. Therefore, if a transition is made to software standby
mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.19 Port A Pin Functions (Modes 1, 2, 7)
Pin
PA
TIOCB
Bit
Initial value
Read/Write
7
/TP
2
7
/
Pin Functions and Selection Method
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA
as follows.
16-bit timer channel 2
settings
PA
NDER7
Pin function
Note: * TIOCB
16-bit timer channel 2
settings
IOB2
IOB1
IOB0
7
DDR
R/W
PA
0
7
2
7
input when IOB2 = 1 and PWM2 = 0.
R/W
PA
0
6
6
(2)
0
0
(1) in table below
R/W
PA
TIOCB
0
5
5
—
—
0
2
Port A data 7 to 0
These bits store data for port A pins
output
R/W
0
1
PA
0
4
4
(1)
—
1
R/W
PA
0
3
3
PA
Rev. 2.0, 06/04, page 295 of 980
7
—
0
input
R/W
PA
0
2
2
(2) in table below
7
TIOCB
DDR select the pin function
PA
7
(2)
—
—
output
1
0
1
2
R/W
PA
input*
0
1
1
TP
7
R/W
PA
output
1
1
0
0
0