HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 492

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI
operates in asynchronous or synchronous mode.
Bit 7
C/A A A A
0
1
For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card
interface.
Bit 7
GM
0
1
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 6—Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In
synchronous mode, the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR
0
1
Note:
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous
mode, the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE
0
1
Note:
* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
* When PE bit is set to 1, an even or odd parity bit is added to transmit data according to
the even or odd parity mode selection by the O/E bit, and the parity bit in receive data
is checked to see that it matches the even or odd mode selected by the O/E bit.
Description
Asynchronous mode
Synchronous mode
Description
The TEND flag is set 12.5 etu after the start bit
The TEND flag is set 11.0 etu after the start bit
Description
8-bit data
7-bit data*
Description
Parity bit not added or checked
Parity bit added and checked*
Rev. 2.0, 06/04, page 463 of 980
(Initial value)
(Initial value)
(Initial value)
(Initial value)