EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 997

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 1 of 4)
February 2011 Altera Corporation
Use manual word alignment
mode.
When should the word aligner
realign?
Use manual bitslipping mode.
Use the Automatic
synchronization state machine
mode.
ALTGX Setting
1
Table 1–12
Plug-In Manager for your ALTGX custom megafunction variation.
The word aligner and rate matcher operations and patterns are pre-configured for
PCIe, GIGE, and XAUI modes, and cannot be altered.
Enabling this option sets the word aligner in Manual
Alignment mode. In Manual Alignment mode, the
word aligner operation is controlled by the input signal
rx_enapatternalign.
Two options are available in manual mode:
■
■
This option sets the word aligner in Bit-Slip mode.
Enabling this option creates an input signal
rx_bitslip to control the word aligner. At every
rising edge of the rx_bitslip signal, the bit slip
circuitry slips one bit into the received data stream,
effectively shifting the word boundary by one bit.
SDI
Because word alignment and framing occur after
de-scrambling, the word aligner in the receiver data
path is not useful in SDI systems. Altera recommends
driving the ALTGX rx_bitslip signal low to prevent
the word aligner from inserting bits in the received
data stream.
This option sets the word aligner in Automatic
Synchronization State Machine mode. This mode is
available only in Single-width mode for 8B/10B
encoded data:
■
or
■
Realign continuously while the
rx_enapatternalign signal is high.
Realign at the rising edge of the
rx_enapatternalign signal.
10-bit PCS-PMA Interface where the 8B/10B
encoder is enabled
10-bit PCS-PMA Interface where the 8B/10B is
disabled but the data is already 8B/10B encoded
lists the available options on the Word Aligner screen of the MegaWizard
Description
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture in
Stratix IV Devices
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture in
Stratix IV Devices
“Word Aligner” section in the
Transceiver Architecture in
Stratix IV Devices
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Architecture in Stratix IV Devices
chapter.
Stratix IV Device Handbook Volume 3
Reference
Transceiver
chapter.
chapter.
chapter.
1–39