EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 69

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
February 2011 Altera Corporation
True Dual-Port Mode
Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called
bi-directional dual-port, this mode allows you to perform any combination of two
port operations: two reads, two writes, or one read and one write at two different
clock frequencies.
Figure 3–12
Figure 3–12. Stratix IV True Dual-Port Memory
Note to
(1) True dual-port memory supports input/output clock mode in addition to independent clock mode.
The widest bit configuration of the M9K and M144K blocks in true dual-port mode is
as follows:
■
■
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
configurations in true dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True Dual-Port Mode)
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9
512 × 18
M9K: 512 × 16-bit (or 512 ×18-bit with parity)
M144K: 4K × 32-bit (or 4K ×36-bit with parity)
Read Port
Figure
3–12:
shows the true dual-port RAM configuration.
8K × 1
v
v
v
v
v
—
—
Table 3–7
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
rden_a
aclr_a
q_a[]
clock_a
4K × 2
v
v
v
v
v
—
—
lists the possible M9K block mixed-port width
2K × 4
v
v
v
v
v
—
—
(Note 1)
addressstall_b
Write Port
address_b[]
byteena_b[]
data_b[ ]
1K × 8
clock_b
wren_b
rden_b
aclr_b
v
v
v
v
v
—
—
q_b[]
Stratix IV Device Handbook Volume 1
512 × 16 1K × 9 512 × 18
v
v
v
v
v
—
—
—
—
—
—
—
v
v
—
—
—
—
—
v
v
3–13