EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 209

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
February 2011 Altera Corporation
OCT Calibration
Figure 6–25
(where N is a calibration block number), you must assert ENAOCT one cycle before
asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before
the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK
cycles to perform OCTRS and OCTRT calibration. You can de-assert ENAOCT one clock
cycle after the last ENASER is de-asserted.
Serial Data Transfer
After you complete calibration, you must serially shift out the 28-bit OCT calibration
codes (14-bit OCT R
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any time by asserting only one ENASER[N] signal at a time. After you de-assert ENAOCT,
wait at least one OCTUSRCLK cycle to enable any ENASER[N] signal to begin serial
transfer. To shift the 28-bit code from the OCT calibration block[N], you must assert
ENASER[N] for exactly 28 OCTUSRCLK cycles. Between two consecutive asserted ENASER
signals, there must be at least one OCTUSRCLK cycle gap.
Figure 6–25. OCT User Mode Signal—Timing Waveform for One OCT Block
Note to
(1) t
After calibrated codes are shifted in serially to each I/O bank, the calibrated codes
must be converted from serial to parallel format before being used in the I/O buffers.
Figure 6–25
calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
de-asserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
s2p
Figure
≥ 25 ns.
OCTUSRCLK
S2PENA_1A
nCLRUSR
ENASER0
ENAOCT
6–25:
shows user mode signal-timing waveforms. To calibrate OCT block[N]
shows the S2PENA signals that can be asserted at any time to update the
S
and 14-bit OCT R
1000 OCTUSRCLK Cycles
Calibration Phase
T
) from each OCT calibration block to the
OCTUSRCLK
(Figure
Cycles
28
Stratix IV Device Handbook Volume 1
6–25).
t s2p
(1)
6–37