EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 837

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
PMA Direct Drive Mode Reset Sequences
Table 4–8. Reset and Power-Down Sequences for Basic (PMA Direct) Drive ×1 Configurations
February 2011 Altera Corporation
Receiver and Transmitter
Receiver and Transmitter
Channel Set Up
Basic (PMA Direct) Drive x1 Mode
As shown in
×4 double-width configuration with CDR in manual lock mode, follow these reset
steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the rx_analogreset and rx_locktorefclk signals asserted and the
3. When the transmitter PLL locks, as indicated by the pll_locked signal going high
4. For the receiver operation, after de-assertion of the busy signal (marker 4), wait for
5. Wait for the rx_pll_locked signal from each channel to go high. The
6. In a PMA Direct drive ×4 double-width configuration, when the rx_pll_locked
7. After assertion of the rx_locktodata signal, from that point onwards, wait for at
The following timing diagram examples are used to describe the reset and power
down sequences for Basic (PMA Direct) drive mode without bonding between the
transceiver channels.
Table 4–8
functional mode.
time between markers 1 and 2).
rx_locktodata signal de-asserted during this time period. After you de-assert the
pll_powerdown signal, the transmitter PLL starts locking to the transmitter input
reference clock.
(marker 3), the transmitter is ready to accept parallel data from the FPGA fabric
and transmitting serial data reliably.
a minimum of two parallel clock cycles to de-assert the rx_analogreset signal.
After the rx_analogreset signal is de-asserted, the receiver CDR of each channel
starts locking to the receiver input reference clock because rx_locktorefclk is
asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at marker 6).
signal of all the channels has gone high, from that point onwards, wait for at least
t
(marker 7). At this point, the receiver CDR of all the channels enters into
lock-to-data mode and starts locking to the received data.
least t
point, all the receivers are ready for transferring valid parallel data into the FPGA
fabric (until this time, Altera recommends that the user logic that processes this
data be under reset).
LTR_LTD_Manual
Automatic lock mode for Basic
(PMA Direct) drive ×1 mode
Manual lock mode for Basic
(PMA Direct) drive ×1 mode
LTD_Manual
lists the reset and power-down sequences for Basic (PMA Direct) drive ×1
Figure
Functional Mode
, then de-assert rx_locktorefclk and assert rx_locktodata
4–17, for the receiver and transmitter channel in PMA Direct drive
(marker 8) for the receiver parallel clock to become stable. At this
“Receiver and Transmitter Channel Set-Up—Receiver
CDR in Automatic Lock Mode” on page 4–32
“Receiver and Transmitter Channel Set-up—Receiver
CDR in Manual Lock Mode” on page 4–34
Stratix IV Device Handbook Volume 2: Transceivers
Refer to
pll_powerdown
(the
4–31