EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 876

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–30
Stratix IV Device Handbook Volume 2: Transceivers
1
1
1
The logical reference index of the CMU0 PLL within a transceiver block is always the
complement of the logical reference index of the CMU1 PLL within the same transceiver
block.
This logical reference index value is stored as logical tx pll, along with the other
transceiver channel settings in the .mif.
The following describes the Clocking/Interface options. The core clocking setup
describes the transceiver core clocks that are the write and read clocks of the transmit
(TX) phase compensation FIFO and the receive (RX) phase compensation FIFO,
respectively. Core clocking is classified as transmitter core clocking and receiver core
clocking.
Transmitter core clocking refers to the clock that is used to write the parallel data from
the FPGA fabric into the Transmit Phase Compensation FIFO. You can use one of the
following clocks to write into the Transmit Phase Compensation FIFO:
■
■
The Clocking/Interface screen is not available for PMA-only channels.
■
■
Consider the following scenario:
■
■
■
Option 1 is applicable in this scenario because it saves clock resources.
tx_coreclk—You can use a clock of the same frequency as tx_clkout from the
FPGA fabric to provide the write clock to the Transmit Phase Compensation FIFO.
If you use tx_coreclk, it overrides the tx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
tx_clkout—The Quartus II software automatically routes tx_clkout to the FPGA
fabric and back into the TX phase compensation FIFO.
Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the write clock to the TX phase compensation FIFOs
of the remaining channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block are of
the same functional mode and data rate, and are reconfigured to the identical
functional mode and data rate.
Four regular transceiver channels configured at 3 Gbps and in the same functional
mode.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
You want to reconfigure all four regular transceiver channels to 1.5 Gbps and vice
versa.
Clocking/Interface Options
Option 1: Share a Single Transmitter Core Clock Between Transmitters
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation