EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 671

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Document Revision History
Table 1–81. Document Revision History (Part 2 of 2)
February 2011 Altera Corporation
June 2009
March 2009
November 2008
May 2008
Date
Version
2.0
3.1
3.0
1.0
■
■
■
■
■
■
■
■
■
Added Offset Cancellation in the Receiver Buffer and Receiver CDR to the Receiver Channel
Datapath section
Initial release.
Updated the “Introduction”, “Auxiliary Transmit (ATX) PLL Block”, “Rate Match (Clock
Rate Compensation) FIFO”, “Transmitter Buffer Electrical Idle”, “PCIe Gen2 (5 Gbps)
Support”, “Reverse Serial Loopback”, and “Reverse Serial Pre-CDR Loopback” sections.
Added new “PCI Express Electrical Gold Test with Compliance Base Board (CBB)”,
“Recommendation When Using the Electrical Idle Inference Block”. and “Rate Match FIFO
in Serial RapidIO Mode” sections.
Added new Figure 1–165.
Updated Table 1–2, Table 1–17, Table 1–32, Table 1–34, and Table 1–52.
Updated Figure 1–7, and Figure 1–165 through Figure 1–168.
Minor text edits.
Reorganized sections.
Added the section “Link Coupling”.
Updated the section “DC-Coupled Links”.
Changes
Stratix IV Device Handbook Volume 2: Transceivers
1–227