EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 578

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–134
Figure 1–109. Receiver Detect, Successfully Detected
Figure 1–110. Receiver Detect, Unsuccessfully Detected
Stratix IV Device Handbook Volume 2: Transceivers
tx_detectrxloopback
pipephydonestatus
powerdown[1:0]
pipestatus[2:0]
tx_detectrxloopback
pipephydonestatus
powerdown[1:0]
pipestatus[2:0]
Figure 1–109
was successfully detected and where a receiver was not detected, respectively.
The LTSSM state machine can enter the polling.compliance substate where the
transmitter is required to transmit a compliance pattern as specified in the PCIe Base
Specification 2.0. The polling.compliance substate is intended to assess if the
transmitter is electrically compliant with the PCIe voltage and timing specifications.
The compliance pattern is a repeating sequence of the following four code groups:
■
■
■
■
/K28.5/
/D21.5/
/K28.5/
/D10.2/
Compliance Pattern Transmission Support
and
Figure 1–110
2'b10 (P1)
2'b10(P1)
show the receiver detect operation where a receiver
3'b000
3'b000
Chapter 1: Transceiver Architecture in Stratix IV Devices
3'b011
February 2011 Altera Corporation
Transceiver Block Architecture