EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 129

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
Clock Output Connections
1
Dedicated clock pins can drive PLLs over dedicated routing; they do not require the
global or regional network. Compensated inputs, which are a subset of dedicated
clock pins, drive PLLs that can only compensate the input delay when a dedicated
clock pin is in the same I/O bank as the PLL used.
PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK
networks. For Stratix IV PLL connectivity to GCLK networks, refer to
Quartus II software automatically assigns PLL clock outputs to RCLK and GCLK
networks.
Table 5–5
Table 5–5. Stratix IV PLL Connectivity to the GCLK Networks
Table 5–6
Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
Note to
(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
RCLK[0..11]
RCLK[12..31]
RCLK[32..43]
RCLK[44..63]
Clock Resource
Clock Network
Table
lists how the PLL clock outputs connect to the GCLK networks.
lists how the PLL clock outputs connect to the RCLK networks.
5–5:
L1
—
—
—
—
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
L1
v
v
L2
—
—
—
v
v
L2
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
—
—
—
L3
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
L3
v
L4
—
—
—
—
v
v
v
L4
—
—
—
—
—
—
—
—
—
—
—
—
v
B1
v
v
v
v
B1
—
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLL Number
PLL Number
B2
v
v
v
v
B2
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R1
—
—
—
—
—
—
—
—
v
v
v
v
—
—
—
—
R1
—
—
—
—
(Note 1)
(Note 1)
Stratix IV Device Handbook Volume 1
R2
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
R2
—
—
v
—
R3
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
(Part 1 of 2)
R3
—
—
v
—
Table
R4
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
R4
—
—
—
—
5–5. The
T1
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
T1
—
—
—
v
v
5–13
T2
—
—
—
—
—
—
—
—
—
—
—
—
T2
—
—
—
v
v
v
v