EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 584

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–140
Stratix IV Device Handbook Volume 2: Transceivers
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If you do not select the Enable electrical idle inference functionality option in the
ALTGX MegaWizard Plug-In Manager, the Electrical Idle Inference module is
disabled. In this case, the rx_signaldetect signal from the signal detect circuitry in
the receiver buffer is inverted and driven as the pipeelecidle signal.
Recommendation When Using the Electrical Idle Inference Block
In a PCIe link, when operating at Gen2 data rate, the downstream device can go into
the Disable state after instruction from the upper layer. Once in the Disable state, the
downstream device must detect an Electrical Idle Exit condition to go into the Detect
state. At this same time, the upstream device can be directed by the upper layer to go
into the Detect state and start transmitting the COM symbols to the downstream
device at Gen 1 data rate.
The Disable and Detect states are different states of the Link Training and Status State
Machine as described by the PCIe Base Specification Rev 2.0.
The COM symbol is an 8B/10B encoded value of K28.5 and is part of the training
sequences TS1 and TS2 as described by the PCIe Base Specification Rev 2.0.
When the Stratix IV GX and GT device is operating as a downstream device at PCIe
Gen 2 data rates and if it goes into the Disable State, the Stratix IV GX and GT receiver
must receive an Electrical Idle Exit condition in order to move out of the Disable state.
For the Stratix IV GX and GT receiver, the Electrical Idle Exit condition is achieved
when COM symbols are received from the upstream device. However, after the
Disable state is achieved by the Stratix IV GX and GT receiver (the downstream
device) during Gen 2 data rate operation, and if at the same time the upstream device
is directed to transition to the Detect state, the upstream device starts to send COM
symbols at Gen 1 data rate. Consequently, the Stratix IV GX and GT receiver (the
downstream device) does not recognize the COM symbols as it is operating at Gen 2
data rate. To avoid this scenario, the Link Training Status State Machine (LTSSM) in
the FPGA fabric of Stratix IV GX and GT receiver (the downstream device) must be
implemented in such a way that whenever the downstream device goes into the
Disable state and the upstream device is directed to go into the Detect state, the
rateswitch signal must be transitioned from high to low. This allows the
Stratix IV GX and GT receiver (the downstream device) to move from Gen 2 to Gen 1
data rate. Subsequently, the Stratix IV GX and GT receiver (the downstream device)
recognizes the COM symbols being sent by the upstream device at Gen 1 data rates
and moves from the Disable state to the Detect state.
The PCIe functional mode supports the following additional features when
configured for 5 Gbps data rate:
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Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate
Dynamically selectable transmitter margining for differential output voltage
control
Dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 dB
PCIe Gen2 (5 Gbps) Support
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture