EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 615

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–137. Rate Match Deletion in GIGE Mode
Figure 1–138. Rate Match Insertion in GIGE Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
rx_rmfifodatainserted
dataout
dataout
datain
datain
In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps adhering to
the rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate matcher deletes or inserts both symbols (/K28.5/ and /D16.2/) of the
/I2/ ordered sets even if it requires deleting only one symbol to prevent the rate
match FIFO from overflowing or under-running. It can insert or delete as many /I2/
ordered sets as necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match
FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric.
Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for
two clock cycles for each deleted and inserted /I2/ ordered set, respectively.
Figure 1–137
required to be deleted. Because the rate match FIFO can only delete /I2/ ordered set,
it deletes two /I2/ ordered sets (four symbols deleted).
Figure 1–138
symbol is required to be inserted. Because the rate match FIFO can only delete /I2/
ordered set, it inserts one /I2/ ordered set (two symbols inserted).
For more information, refer to
page
Rate Match FIFO
1–77.
Dx.y
Dx.y
Dx.y
Dx.y
First /I2/ Skip Ordered Set
shows an example of rate match FIFO deletion where three symbols are
shows an example of rate match FIFO insertion in the case where one
First /I2/ Ordered Set
K28.5
K28.5
K28.5
K28.5
D16.2
D16.2
D16.2
D16.2
/I2/ SKIP Symbol Deleted
“Rate Match (Clock Rate Compensation) FIFO” on
Second /I2/ Skip Ordered Set
Second /I2/ Ordered Set
Dx.y
K28.5
K28.5
K28.5
D16.2
D16.2
D16.2
Stratix IV Device Handbook Volume 2: Transceivers
K28.5
K28.5
Third /I2/ Skip Ordered Set
D16.2
D16.2
Dx.y
Dx.y
1–171