EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 576

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–132
Table 1–48. Supported Features in PCIe Mode (Part 2 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Receiver status encoding
Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate
Dynamically selectable transmitter margining for differential output
voltage control
Dynamically selectable transmitter buffer de-emphasis of -3.5 db and
-6 dB
1
PCIe Interface
In PCIe mode, each channel has a PCIe interface block that transfers data, control, and
status signals between the PHY-MAC layer and the transceiver channel PCS and PMA
blocks. The PCIe interface block is compliant to version 2.0 of the PCIe specification. If
you use the PCIe hard IP block, the PHY-MAC layer is implemented in the hard IP
block. Otherwise, the PHY-MAC layer can be implemented using soft IP in the FPGA
fabric.
The PCIe interface block is only used in PCIe mode and cannot be bypassed.
Besides transferring data, control, and status signals between the PHY-MAC layer
and the transceiver, the PCIe interface block implements the following functions
required in a PCIe-compliant physical layer device:
■
■
■
■
■
■
When the input signal tx_forceelecidle is asserted high, the PCIe interface block
puts the transmitter buffer in that channel in the electrical idle state. During electrical
idle, the transmitter buffer differential and common mode output voltage levels are
compliant to the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
Figure 1–108
signal and the transmitter buffer output on the tx_dataout port. Time T1 taken from
the assertion of the tx_forceelecidle signal to the transmitter buffer reaching
electrical idle voltage levels is pending characterization. Once in the electrical idle
state, the PCIe protocol requires the transmitter buffer to stay in electrical idle for a
minimum of 20 ns for both Gen1 and Gen2 data rates.
Forces the transmitter buffer in electrical idle state
Initiates the receiver detect sequence
8B/10B encoder disparity control when transmitting compliance pattern
Manages the PCIe power states
Indicates the completion of various PHY functions; for example, receiver detection
and power state transitions on the pipephydonestatus signal
Encodes the receiver status and error conditions on the pipestatus[2:0] signal as
specified in the PCIe specification
Transmitter Buffer Electrical Idle
Feature
shows the relationship between the assertion of the tx_forceelecidle
Chapter 1: Transceiver Architecture in Stratix IV Devices
2.5 Gbps
(Gen1)
v
—
—
—
February 2011 Altera Corporation
Transceiver Block Architecture
5 Gbps
(Gen2)
v
v
v
v