EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 218

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

6–46
Figure 6–35. Mini-LVDS I/O Standard Termination
Note to
(1) The R
Design Considerations
Stratix IV Device Handbook Volume 1
Termination
Termination
On-Board
External
OCT
Figure
S
I/O Bank Restrictions
and R
6–35:
f
P
1
Transmitter
values are pending characterization.
Transmitter
Mini-LVDS
Stratix IV devices support the mini-LVDS output standard with data rates up to
340 Mbps using LVDS output buffer types. For transmitters, use two single-ended
output buffers with external one- or three-resistor networks, as shown in
The one-resistor topology is for data rates up to 200 Mbps. The three-resistor topology
is for data rates above 200 Mbps. The row I/O banks support mini-LVDS output using
true LVDS output buffers without an external resistor network.
A resistor network is required to attenuate the LVDS output voltage swing to meet the
mini-LVDS specifications. You can modify the three-resistor network values to reduce
power or improve noise margin. The resistor values chosen must satisfy
on page
Altera recommends that you perform additional simulations using IBIS models to
validate that custom resistor values meet the RSDS requirements.
For more information about the mini-LVDS I/O standard, see the mini-LVDS
Specification from the Texas Instruments website at www.ti.com.
Although Stratix IV devices feature various I/O capabilities for high-performance
and high-speed system designs, there are several other design considerations that
require your attention to ensure the success of your designs.
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix IV devices.
One-Resistor Network (mini-LVDS_E_1R)
≤1 inch
≤1 inch
6–45.
R
R
P
P
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100 Ω
Stratix IV OCT
(Note 1)
Receiver
Receiver
Transmitter
Transmitter
Three-Resistor Network (mini-LVDS_E_3R)
Chapter 6: I/O Features in Stratix IV Devices
R S
R S
≤1 inch
≤
R S
R S
1 inch
R
P
R
P
February 2011 Altera Corporation
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
Design Considerations
100
Equation 6–1
Figure
Stratix IV OCT
Ω
Receiver
Receiver
6–35.