EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 600

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–156
Figure 1–123. Stratix IV GX and GT XAUI Mode Configuration
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
PMA-PCS Interface
Fabric-Transceiver
Encoder/Decoder
Fabric-Transceiver
TX PCS Latency
Interface Frequency
Functional Modes
Low-Latency PCS
RX PCS Latency
Channel Bonding
Data Rate (Gbps)
Rate Match FIFO
Functional Mode
Deskew FIFO
(Pattern Length)
Byte Ordering
Interface Width
Byte SerDes
Word Aligner
8B/10B
FPGA
(MHz)
Width
FPGA
Figure 1–123
devices.
8-bit
Single
Width
10-bit
shows the XAUI mode configuration supported in Stratix IV GX and GT
Basic
16-bit
Double
Width
Stratix IV GX and GT Configurations
20-bit
10-bit
PIPE
10-bit
XAUI
Synchronization
(10-Bit/K28.5/)
State Machine
3.125 - 3.75
Automatic
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
XAUI
156.25-
16-Bit
187.5
4.5 - 6
14.5 -
GIGE
10-bit
x4
Chapter 1: Transceiver Architecture in Stratix IV Devices
18
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
February 2011 Altera Corporation
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit