EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 210

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

6–38
Figure 6–26. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
Notes to
(1) ts2p ≥ 25 ns.
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
Termination Schemes for I/O Standards
Stratix IV Device Handbook Volume 1
Figure
Single-Ended I/O Standards Termination
S2PENA_1A (2)
S2PENA_2A (3)
OCTUSRCLK
6–26:
ENASER0
ENASER1
nCLRUSR
1
ENAOCT
Example of Using Multiple OCT Calibration Blocks
Figure 6–26
and R
asserting the ENASER signals at different times. ENAOCT must remain asserted while any
calibration is ongoing. You must set nCLRUSR low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In
time to initialize OCT calibration block 0, this does not affect OCT calibration block 1,
whose calibration is already in progress.
R
If only R
signal only requires to be asserted for 240 OCTUSRCLK cycles.
You must assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer.
The following sections describe the different termination schemes for the I/O
standards used in Stratix IV devices.
Voltage-referenced I/O standards require both an input reference voltage, V
termination voltage, V
termination voltage of the transmitting device.
Figure 6–27
Stratix IV devices.
S
Calibration
T
calibration. Calibration blocks can start calibrating at different times by
S
calibration is used for an OCT calibration block, its corresponding ENASER
shows a signal timing waveform for two OCT calibration blocks doing R
and
1000
CY CLE S
OCTUSRCLK
Figure 6–28
Calibration Phase
1000
TT
CY CLE S
. The reference voltage of the receiving device tracks the
OCTUSRCLK
show the details of SSTL and HSTL I/O termination on
Figure
6–26, when you set nCLRUSR to 0 for the second
28
OCTUSRCLK
CY CLE S
Chapter 6: I/O Features in Stratix IV Devices
ts2p (1)
28
Termination Schemes for I/O Standards
OCTUSRCLK
CY CLE S
February 2011 Altera Corporation
ts2p (1)
REF
, and a
S