EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 930

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–84
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 9 of 13)
Stratix IV Device Handbook Volume 2: Transceivers
rx_eqdcgain[2:0] (1),
tx_vodctrl_out[2:0]
tx_preemp_0t_out[4:0]
tx_preemp_1t_out[4:0]
tx_preemp_2t_out[4:0]
rx_eqctrl_out[3:0]
rx_eqdcgain_out[2:0]
Port Name
(2)
Output
Output
Output
Output
Output
Output
Output
Input/
Input
This is an optional equalizer DC gain write control.
The width of this signal is fixed to 3 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 3 bits per channel.
For more information, refer to
Controls” on page
The following values are the legal settings allowed for this signal:
3’b000 => 0 dB
3’b001 => 3 dB
3’b010 => 6 dB
3’b011 => 9 dB
3’b100 => 12 dB
All other values => N/A
For more information, refer to the “Programmable Equalization and
DC Gain” section of the
Devices
This is an optional transmit V
reads out the value written into the V
of this output signal depends on the number of channels controlled
by the dynamic reconfiguration controller.
This is an optional pre-tap, pre-emphasis read control signal. This
signal reads out the value written by its input control signal. The
width of this output signal depends on the number of channels
controlled by the dynamic reconfiguration controller.
This is an optional first post-tap, pre-emphasis read control signal.
This signal reads out the value written by its input control signal.
The width of this output signal depends on the number of channels
controlled by the dynamic reconfiguration controller.
This is an optional second post-tap pre-emphasis read control
signal. This signal reads out the value written by its input control
signal. The width of this output signal depends on the number of
channels controlled by the dynamic reconfiguration controller.
This is an optional read control signal to read the equalization
setting of the ALTGX instance. The width of this output signal
depends on the number of channels controlled by the dynamic
reconfiguration controller.
This is an optional equalizer DC gain read control signal. This signal
reads out the settings of the ALTGX instance DC gain. The width of
this output signal depends on the number of channels controlled by
the dynamic reconfiguration controller.
chapter.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
5–13.
Transceiver Architecture in Stratix IV
Description
OD
Dynamic Reconfiguration Controller Port List
“Dynamically Reconfiguring PMA
read control signal. This signal
OD
February 2011 Altera Corporation
control register. The width
(Note
3),
(4)