EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 127
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Table 5–2. Clock Input Pin Connectivity to the GCLK Networks
Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)
February 2011 Altera Corporation
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
RCLK [0, 4, 6, 10]
RCLK [1, 5, 7, 11]
RCLK [2, 8]
RCLK [3, 9]
RCLK [13, 17, 21, 23,
27, 31]
RCLK [12, 16, 20, 22,
26, 30]
RCLK [15, 19, 25, 29]
RCLK [14, 18, 24, 28]
RCLK [35, 41]
Clock Resources
Clock Resource
PLL Clock Outputs
Stratix IV PLLs can drive both GCLK and RCLK networks, as described in
on page 5–13
Table 5–2
Table 5–3
Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to
create a dual-regional clock network.
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1
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0
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lists the connection between the dedicated clock input pins and GCLKs.
lists the connectivity between the dedicated clock input pins and RCLKs in
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and
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Table 5–6 on page
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5
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6
CLK (p/n Pins)
5–13.
v
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6
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v
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CLK (p/n Pins)
v
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7
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10
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Stratix IV Device Handbook Volume 1
11
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Table 5–5
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5–11
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