EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 169

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Document Revision History
Document Revision History
Table 5–18. Document Revision History (Part 1 of 2)
February 2011 Altera Corporation
February 2011
March 2010
November 2009
June 2009
April 2009
Date
PLL Specifications
f
Version
For information about PLL timing specifications, refer to the
Characteristics for Stratix IV Devices
Table 5–18
3.0
3.2
3.1
2.3
2.2
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Updated the
Feedback
Updated
Updated
Applied new template.
Minor text edits.
Updated Table 5–3.
Updated notes to Figure 5–2, Figure 5–3, Figure 5–4, and Figure 5–9.
Added a note to Table 5–5 and Table 5–6.
Added two notes to Table 5–4.
Updated Figure 5–43.
Updated the “Dynamic Phase-Shifting” section.
Minor text edits.
Updated Table 5–1 and Table 5–7.
Updated “Clock Networks in Stratix IV Devices”, “Periphery Clock Networks”, and
“Cascading PLLs” sections.
Added Figure 5–5, Figure 5–6, Figure 5–7, Figure 5–8, and Figure 5–9.
Added “Clock Sources Per Region” section.
Updated Figure 5–40.
Removed EP4SE110, EP4SE290, and EP4SE680 devices.
Added EP4S40G2, EP4S100G2, EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, and
EP4SE820 devices.
Updated Table 5–7.
Updated the “PLL Reconfiguration Hardware Implementation” and “Zero-Delay Buffer
Mode” sections.
Added introductory sentences to improve search ability.
Removed the Conclusion section.
Minor text edits.
Updated Table 5–1 and Table 5–7.
Updated Figure 5–3 and Figure 5–4.
Updated the “Periphery Clock Networks” section.
lists the revision history for this chapter.
Table 5–4
Figure
Modes”, and
“Clock Input Connections to the PLLs”,“PLL Clock I/O
5–26,
and
Figure
“Clock Switchover”
Table
5–40, and
5–8.
chapter.
Changes
Figure
sections.
5–43.
Stratix IV Device Handbook Volume 1
DC and Switching
Pins”,
“Clock
5–53