EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 809

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
User Reset and Power-Down Signals
Table 4–2. Transceiver Block Power-Down Signals
Table 4–3. Blocks Affected by Reset and Power-Down Signals (Part 1 of 2)
February 2011 Altera Corporation
pll_powerdown
gxb_powerdown
pll_locked
rx_pll_locked
rx_freqlocked
busy
Note to
(1) The refclk (refclk0 or refclk1) buffer is not powered down by this signal.
CMU PLLs
Transmitter Phase
Compensation FIFO
Transceiver Block
Table
Blocks Affected by the Reset and Power-Down Signals
Signal
4–2:
f
1
(1)
(1)
Table 4–2
For more information about offset cancellation, refer to the
Stratix IV Devices
If none of the channels is instantiated in a transceiver block, the Quartus
automatically powers down the entire transceiver block.
Table 4–3
rx_digitalreset
Each transceiver block has two CMU PLLs. Each CMU PLL has this dedicated power-down
signal. This signal powers down the CMU PLLs that provide high-speed serial and
low-speed parallel clocks to the transceiver channels.
Powers down the entire transceiver block. When this signal is asserted, it powers down:
■
■
This signal operates independently from the other reset signals and is common to the
transceiver block.
A status signal. Indicates the status of the transmitter PLL.
■
A status signal.
■
A status signal. Indicates the status of the receiver CDR lock mode.
■
■
A status signal. An output from the ALTGX_RECONFIG block indicates the status of the
dynamic reconfiguration controller. This signal remains low for the first reconfig_clk
clock cycle after power up. It then is asserted from the second reconfig_clk clock cycle.
Assertion on this signal indicates that the offset cancellation process is being executed on
the receiver buffer as well as the receiver CDR. When this signal is de-asserted, it indicates
that offset cancellation is complete.
—
—
lists the power-down signals available for each CMU PLL transceiver block.
lists the blocks that are affected by specific reset and power-down signals.
the PCS and PMA in all the transceiver channels
the CMU PLLs
A high level—the transmitter PLL is locked to the incoming reference clock frequency.
When pll_locked is high, tx_digitalreset must always be asserted. To de-assert
tx_digitalreset, follow the initialization reset sequence for your specific mode.
A high level—the receiver CDR is locked to the incoming reference clock frequency.
A high level—the receiver is in lock-to-data (LTD) mode.
A low level—the receiver CDR is in lock-to-reference (LTR) mode. In automatic lock
mode, when rx_freqlocked is high, rx_digitalreset must always be asserted. To
de-assert rx_digitalreset, follow the initialization reset sequence for your specific
mode.
chapter.
rx_analogreset
—
—
tx_digitalreset
Description
—
v
Stratix IV Device Handbook Volume 2: Transceivers
pll_powerdown
v
—
Dynamic Reconfiguration in
gxb_powerdown
®
II software
v
v
4–3