EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 298

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–20
Stratix IV Device Handbook Volume 1
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DPA circuitry does not require a fixed training pattern to lock to the optimum phase
out of the eight phases. After reset or power up, DPA circuitry requires transitions on
the received data to lock to the optimum phase. An optional output port,
RX_DPA_LOCKED, is available to indicate an initial DPA lock condition to the optimum
phase after power up or reset. This signal is not de-asserted if the DPA selects a new
phase out of the eight clock phases to sample the received data. Do not use the
rx_dpa_locked signal to determine a DPA loss-of-lock condition. Use data checkers
such as a cyclic redundancy check (CRC) or diagonal interleaved parity (DIP-4) to
validate the data.
An independent reset port, RX_RESET, is available to reset the DPA circuitry. DPA
circuitry must be retrained after reset.
The DPA block is bypassed in non-DPA mode.
Synchronizer
The synchronizer is a 1 bit wide and 6 bit deep FIFO buffer that compensates for the
phase difference between DPA_diffioclk, which is the optimal clock selected by the
DPA block, and LVDS_diffioclk, which is produced by the left and right PLL. The
synchronizer can only compensate for phase differences, not frequency differences
between the data and the receiver’s input reference clock.
An optional port, RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first locks to the
incoming data. Altera recommends using RX_FIFO_RESET to reset the synchronizer
when the DPA signals a loss-of-lock condition and the data checker indicates
corrupted received data.
The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If the DPA is enabled,
the received data is captured with different clock phases on each channel. This may
cause the received data to be misaligned from channel to channel. To compensate for
this channel-to-channel skew and establish the correct received word boundary at
each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver
independently controlled from the internal logic. The data slips one bit on the rising
edge of RX_CHANNEL_DATA_ALIGN. The requirements for the RX_CHANNEL_DATA_ALIGN
signal include:
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The minimum pulse width is one period of the parallel clock in the logic array.
The minimum low time between pulses is one period of the parallel clock.
This is an edge-triggered signal.
Valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
February 2011 Altera Corporation
Differential Receiver