EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1065

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
Dynamic Reconfiguration
Table 3–2. MegaWizard Plug-In Manager Options (Page 4) (Part 2 of 2)
February 2011 Altera Corporation
Write Control
Read Control
ALTGX_RECONFIG
Setting
The PMA control ports available to write various analog
settings to the transceiver channels controlled by the
dynamic reconfiguration controller are as follows:
■
■
■
■
■
■
These are optional signals. The signal widths are based on
the setting you entered for the What is the number of
channels controlled by the reconfig controller? option
and whether you enabled the Use
'logical_channel_address' port for Analog controls
reconfiguration option. The port width is also determined
by the Use the same control signal for all channels
option.
At least one of these PMA control ports must be enabled
to configure and use the dynamic reconfiguration
controller.
The PMA control ports available to read the existing values
from the transceiver channels controlled by the dynamic
reconfiguration controller are as follows:
■
■
■
■
■
■
These are optional signals. The signal widths are based on
the setting you entered for the What is the number of
channels controlled by the reconfig controller? option
and whether you enabled the Use
'logical_channel_address' port for Analog controls
reconfiguration option.
The PMA controls are available for selection only if you
select the corresponding write control. Read and write
transactions cannot be performed simultaneously.
tx_vodctrl—V
tx_preemp_0t—Pre-emphasis control pre-tap; 5 bits
per channel
tx_preemp_1t—Pre-emphasis control 1st post-tap;
5 bits per channel
tx_preemp_2t—Pre-emphasis control 2nd post-tap;
5 bits per channel
rx_eqdcgain—Equalizer DC gain; 3 bits per channel
rx_eqctrl—Equalizer control; 4 bits per channel
tx_vodctrl_out—V
tx_preemp_0t_out—Pre-emphasis control pre-tap;
5 bits per channel
tx_preemp1t_out—Pre-emphasis control 1st
post-tap; 5 bits per channel
tx_preemp_2t_out—Pre-emphasis control 2nd
post-tap; 5 bits per channel
rx_eqdcgain_out—Equalizer DC gain; 3 bits per
channel
rx_eqctrl_out—Equalizer control; 4 bits per channel
OD
; 3 bits per channel
Description
OD
; 3 bits per channel
“Dynamically Reconfiguring PMA
Controls” section of the
Reconfiguration in Stratix IV
Devices
Stratix IV Device Handbook Volume 3
chapter.
Reference
Dynamic
3–9