EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1010

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–52
Table 1–16. MegaWizard Plug-In Manager Options (PCIe 1) (Part 2 of 2)
Stratix IV Device Handbook Volume 3
Create an rx_patterndetect
output port to indicate pattern
detected.
Create an rx_ctrldetect port to
indicate 8B/10B decoder has
detected a control code.
Create a tx_detectrxloop input
port as Receiver detect or loopback
enable, depending on the power
state.
Create a tx_forceelecidle input
port to force the Transmitter to send
Electrical Idle signals.
Create a
tx_forcedispcompliance input
port to force negative running
disparity.
Create a tx_invpolarity port to
allow Transmitter polarity inversion.
Note to
(1) Refer to the table 'Power States and Functions Allowed in Each Power State' in the PIPE Interface section in the
Stratix IV Devices
Table
ALTGX Setting
1–16:
chapter.
This is an output status signal that the word aligner
forwards to the FPGA fabric to indicate that the word
alignment pattern programmed has been detected in
the current word boundary. The signal width is 1 and
2 bits for a channel width of 8 bits and 16 bits,
respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is a
data or control code group on this port.
If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the
IEEE802.3 specification, this signal is driven high. If
the received 10-bit code group is a data code group
(/Dx.y/), this signal is driven low. The signal width is
1 and 2 bits for a channel width of 8 bits and 16 bits,
respectively.
Depending on the power-down mode, asserting this
signal enables either the receiver detect operation or
Loopback mode.
Enabling this port sets the transmitter buffer in
electrical idle mode. This port is available in all PCIe
power-down modes and has a specific use in each
mode.
A high level on this port forces the associated
parallel transmitter data on the tx_datain port to
be transmitted with negative current running
disparity.
■
■
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this option
when the positive and negative signals of the
differential output from the transmitter
(tx_dataout) are erroneously swapped on the
board.
For 8-bit transceiver channel width
configurations, you must drive
tx_forcedispcompliance[1:0] high in the
same parallel clock cycle as the first /K28.5/ of
the compliance pattern on the tx_datain port.
For 16-bit transceiver channel width
configurations, you must drive only the LSB of
tx_forcedispcompliance[1:0]high in the
same parallel clock cycle as /K28.5/D21.5/ of the
compliance pattern on the tx_datain port.
(1)
(1)
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Automatic Synchronization
State Machine Mode Word
Aligner with 10-bit PMA-PCS
Interface Mode” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Decoder” section in
the
in Stratix IV Devices
“Receiver Detection” and
“PCIe Reverse Parallel
Loopback” section in the
Transceiver Architecture in
Stratix IV Devices
“Transmitter Buffer Electrical
Idle” section in the
Transceiver Architecture in
Stratix IV Devices
“Compliance Pattern
Transmission Support”
section in the
Architecture in Stratix IV
Devices
“Transmitter Polarity
Inversion” section in the
Transceiver Architecture in
Stratix IV Devices
February 2011 Altera Corporation
Transceiver Architecture
Transceiver Architecture in
chapter.
Reference
Transceiver
Protocol Settings
chapter.
chapter.
chapter.
chapter.
chapter.