EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1127
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number:
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Manufacturer:
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Part Number:
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)—Preliminary
April 2011 Altera Corporation
f
f
f
t
f
f
t
t
t
t
f
t
t
f
t
t
t
t
IN
INPFD
VCO
EINDUTY
OUT
OUT_EXT
OUTDUTY
FCOMP
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
CLBW
PLL_PSERR
ARESET
INCCJ
OUTPJ_DC
Symbol
(2)
(4),
(6)
(5)
Input clock frequency (–2/–2x speed grade)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
PLL VCO operating range (–2 speed grade)
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–2/–2x speed grade)
Output frequency for internal global or regional clock
(–3 speed grade)
Output frequency for internal global or regional clock
(–4 speed grade)
Output frequency for external clock output (–2 speed grade)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
Time required to reconfigure scan chain
Time required to reconfigure phase shift
scanclk frequency
Time required to lock from end-of-device configuration or
de-assertion of areset
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on the areset signal
Input clock cycle to cycle jitter (F
Input clock cycle to cycle jitter (F
Period Jitter for dedicated clock output (F
Period Jitter for dedicated clock output (F
PLL Specifications
Table 1–34
commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
lists the Stratix IV PLL specifications when operating in both the
Parameter
REF
REF
(8)
< 100 MHz)
≥ 100 MHz)
OUT
OUT
≥ 100 MHz)
< 100 MHz)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Min
600
600
600
40
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
5
5
5
5
Typ
3.5
0.3
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
1
4
800
717
717
800
717
717
800
717
717
1600
1300
1300
±750
Max
0.15
17.5
325
100
±50
175
60
55
10
—
—
—
—
—
—
1
1
(1)
(1)
(1)
(3)
(3)
(3)
(3)
(3)
(3)
mUI (p-p)
UI (p-p)
ps (p-p)
ps (p-p)
scanclk
scanclk
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ns
ps
ns
%
%
1–45
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