EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 531

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–72. Rate Match Deletion in Basic Double-Width Mode
Figure 1–73. Rate Match Insertion in Basic Double-Width Mode
February 2011 Altera Corporation
rx_rmfifodatainserted
rx_rmfifodatadeleted
dataout[19:0]
datain[19:10]
dataout[9:0]
datain[9:0]
datain[19:10]
dataout[19:0]
dataout[9:0]
datain[9:0]
The rate match FIFO cannot delete the two skip patterns in this skip cluster because
they do not appear in the same clock cycle. The second skip cluster has a /K28.5/
control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip
patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/
skip patterns (for a total of four skip patterns deleted) from the second skip cluster to
meet the three skip pattern deletion requirement.
Figure 1–73
skip patterns are required to be inserted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a
clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle.
The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet the three
skip pattern insertion requirement.
Dx.y
Dx.y
Dx.y
Dx.y
Dx.y
Dx.y
Dx.y
Dx.y
shows an example of rate match FIFO insertion in the case where three
K28.0
K28.5
K28.0
K28.5
First Skip Cluster
K28.0
K28.5
K28.5
K28.0
First Skip Cluster
Dx.y
Dx.y
K28.0
K28.0
K28.0
K28.0
Dx.y
Dx.y
K28.5
Dx.y
K28.0
K28.0
K28.5
K28.5
Dx.y
Second Skip Cluster
Dx.y
Second Skip Cluster
K28.0
K28.0
Dx.y
Dx.y
Two Pairs of Skip Patterns
K28.0
K28.0
Dx.y
Dx.y
Stratix IV Device Handbook Volume 2: Transceivers
Deleted
K28.0
K28.0
K28.5
Dx.y
K28.0
K28.0
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
1–87