EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 658

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–214
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 3 of 7)
Stratix IV Device Handbook Volume 2: Transceivers
Deskew FIFO
rx_channelaligned
Rate Match (Clock Rate Compensation) FIFO
rx_
rmfifodatainserted
rx_rmfifodatadeleted
rx_rmfifofull
rx_rmfifoempty
Port Name
Output
Output
Output
Output
Output
Output
Input/
coreclkout for
coreclkout for
coreclkout for
coreclkout for
Synchronous to
Synchronous to
Synchronous to
Synchronous to
Synchronous to
rx_clkout or
bonded modes.
rx_clkout or
rx_clkout or
rx_clkout or
rx_clkout for
rx_clkout for
bonded modes
rx_clkout for
bonded modes
rx_clkout for
bonded modes
Clock Domain
coreclkout.
coreclkout.
coreclkout.
coreclkout.
coreclkout
non-bonded
non-bonded
non-bonded
non-bonded
clock signal
modes.
modes.
modes.
modes.
XAUI deskew FIFO channel aligned indicator.
■
■
■
Rate match FIFO insertion status indicator.
■
Rate match FIFO deletion status indicator.
■
Rate match FIFO full status indicator.
■
■
■
Rate match FIFO empty status indicator.
■
■
■
Available only in XAUI mode.
A high level—the XAUI deskew state
machine is either in ALIGN_ACQUIRED_1,
ALIGN_ACQUIRED_2, ALIGN_ACQUIRED_3,
or ALIGN_ACQUIRED_4 state, as specified in
the PCS deskew state diagram in the IEEE
P802.3ae specification.
A low level—the XAUI deskew state machine
is either in LOSS_OF_ALIGNMENT,
ALIGN_DETECT_1, ALIGN_DETECT_2, or
ALIGN_DETECT_3 state, as specified in the
PCS deskew state diagram in the IEEE
P802.3ae specification.
A high level—the rate match pattern byte
has inserted to compensate for the PPM
difference in reference clock frequencies
between the upstream transmitter and the
local receiver.
A high level—the rate match pattern byte got
deleted to compensate for the PPM
difference in reference clock frequencies
between the upstream transmitter and the
local receiver.
A high level indicates that the rate match
FIFO is full.
Without byte serializer —driven a minimum
of two recovered clock cycles.
With byte serializer—driven a minimum of
three recovered clock cycles.
A high level—the rate match FIFO is empty.
Without byte serializer—driven a minimum
of two recovered clock cycles.
With byte serializer—driven a minimum of
three recovered clock cycles.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Transceiver
Channel
Channel
Channel
Channel
Scope
block