EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 47

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–9. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is
February 2011 Altera Corporation
not available.
Figure
2–9:
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(1)
Extended LUT Mode
Use extended LUT mode to implement a specific set of seven-input functions. The set
must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs.
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in
These functions often appear in designs as “if-else” statements in Verilog HDL or
VHDL code.
This input is available
for register packing.
Figure 2–9
5-Input
5-Input
LUT
LUT
shows the template of supported seven-input functions using
combout0
D
Figure 2–9
reg0
Q
occur naturally in designs.
To general or
To general or
local routing
local routing
Stratix IV Device Handbook Volume 1
2–11