EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 814

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

4–8
Figure 4–4. Sample Reset Sequence for Four Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
Figure
pll_powerdown
LTD_Auto
Reset Signals
pll _ powerdown
rx _analogreset
rx_freqlocked[0]
rx_freqlocked[3]
tx _digitalreset
rx _digitalreset
4–4:
duration, refer to the
pll
_
locked
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in automatic lock mode, use the reset
sequence shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
3
4
Figure
Minimum of Two Parallel Clock Cycles
5
4–4.
6
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
t
LTD_Auto (2)
chapter.
chapter.
8
February 2011 Altera Corporation
Transceiver Reset Sequences