EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 407

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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SIV51011-3.2
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51011-3.2
f
1
1
This chapter describes how to use the error detection cyclical redundancy check
(CRC) feature when a Stratix
errors. The purpose of the error detection CRC feature in the Stratix IV device is to
detect a flip in any of the configuration random access memory (CRAM) bits in
Stratix IV devices due to a soft error. With the error detection circuitry, you can
continuously verify the integrity of the configuration CRAM bits.
In critical applications such as avionics, telecommunications, system control, and
military applications, it is important to be able to do the following:
The error detection feature is enhanced in the Stratix IV device family. Similar to
Stratix III devices, the error detection and recovery time for single-event upset (SEU)
in Stratix IV devices is reduced when compared with Stratix II devices.
For more information about test methodology for enhanced error detection in
Stratix IV devices, refer to
using CRC in Altera FPGA
Dedicated circuitry is built into Stratix IV devices and consists of a CRC error
detection feature that optionally checks for SEUs continuously and automatically.
For Stratix IV devices, the error detection CRC feature is provided in the Quartus
software version 8.0 and onwards.
Using error detection CRC for the Stratix IV device family has no impact on fitting or
performance of your device.
This chapter contains the following sections:
Confirm that the configuration data stored in a Stratix IV device is correct
Alert the system to the occurrence of a configuration error
“Error Detection Fundamentals” on page 11–2
“Configuration Error Detection” on page 11–2
“User Mode Error Detection” on page 11–2
“Error Detection Pin Description” on page 11–5
“Error Detection Block” on page 11–6
“Error Detection Timing” on page 11–8
“Recovering From CRC Errors” on page 11–11
11. SEU Mitigation in Stratix IV Devices
Devices.
AN 539: Test Methodology of Error Detection and Recovery
®
IV device is in user mode and recovers from CRC
Subscribe
®
II

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