EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 312

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–34
Figure 8–27. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Stratix IV Device Handbook Volume 1
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
Figure 8–27
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates that the LVDS receiver can sample the data properly, whereas a
negative RSKM indicates that it cannot.
shows the relationship between the RSKM, TCCS, and the receiver’s SW.
TCCS
RSKM
RSKM
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Time Unit Interval (TUI)
Clock Placement
Falling Edge
SW
Internal
TUI
SW
Clock
RSKM
RSKM
TCCS
Source-Synchronous Timing Budget
February 2011 Altera Corporation
TCCS
2