EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 562

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–118
Figure 1–99. Transceiver Configurations in Basic Double-Width Mode with a 16-Bit PMA-PCS Interface for Stratix IV GT
Devices
Note to
(1) The maximum data rate specification shown in
Stratix IV Device Handbook Volume 2: Transceivers
other speed grades offered, refer to the
Figure
(FPGA Fabric-Transceiver
(1)
(FPGA Fabric-Transceiver
(1)
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
Interface Frequency
TX PCS Latency
Interface Frequency
RX PCS Latency
Data Rate (Gbps)
1–99:
Low-Latency PCS
Data Rate (Gbps)
Channel Bonding
Rate Match FIFO
Encoder/Decoder
Interface Width
(Pattern Length)
FPGA Fabric-
FPGA Fabric-
Interface Width
FPGA Fabric-
Byte Ordering
Transceiver
Transceiver
Word Aligner
Byte SerDes
Transceiver
PMA-PCS/Fabric
PMA-PCS
Interface Width
(MHz)
Functional
8B/10B
Modes
8-bit
Disabled
1.0 - 4.0
Disabled
Single
Width
16-bit
155 .5 -
11 - 13
250
5 - 6
Manual Alignment
10-bit
(8-, 16-, 32-bit)
DC and Switching Characteristics
Disabled
Disabled
Basic
Disabled
6.5 - 8.5
203.125
32-bit
77.75 –
16-bit
4 - 5.5
Figure 1–99
Enabled
Double
1.0 - 6.5
Width
Disabled
20-bit
6.5 - 8.5
Enabled
(Note 1)
203.125
77.75 –
32-bit
Stratix IV GT Configurations
4 - 5.5
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
1.0 - 4.0
155 .5 -
11 - 13
16-bit
250
5 - 6
(8-, 16-, 32-bit)
Disabled
Disabled
Bit-Slip
Basic Double Width
16-bit PMA-PCS
Interface Width
Disabled
Enabled
1.0 - 6.5
x1, x4, x8
1.0 – 8.5
203.125
32-bit
77.75 –
6.5 - 8.5
chapter.
4 - 5.5
PIPE
10-bit
Chapter 1: Transceiver Architecture in Stratix IV Devices
XAUI
10-bit
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
Disabled
Disabled
1.0 - 4.0
155.5 -
16-bit
3 - 4
250
4 - 5
16-bit
Disabled
Disabled
Disabled
Enabled
(OIF)
February 2011 Altera Corporation
CEI
1.0 - 8.5
Disabled
Enabled
Transceiver Block Architecture
265.625
32-bit
77.75 –
10-bit
4 - 5.5
3 - 4.5
SDI
10-Bit
Deterministic
Latency
20-Bit