EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 820

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

4–14
Figure 4–7. Sample Reset Sequence for Eight Receiver and Transmitter Channels—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
Output Status Signals
CDR Control Signals
4–7:
rx_locktorefclk[0]
rx_locktorefclk[3]
rx_locktodata[0]
rx_locktodata[3]
Reset Signals
pll _ powerdown
rx _analogreset
rx_pll_locked[0]
tx _digitalreset
rx _digitalreset
rx_pll_locked[7]
duration, refer to the
duration, refer to the
pll _ locked
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For Basic ×8
functional mode, with the receiver CDR in manual lock mode, use the reset sequence
shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
Figure
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
4–7.
3
Minimum of
4
5
Two Parallel Clock Cycles
6
7
7
t
Chapter 4: Reset Control and Power Down in Stratix IV Devices
LTR_LTD_Manual (2)
t
LTD_Manual (3)
8
8
8
8
chapter.
chapter.
chapter.
9
February 2011 Altera Corporation
Transceiver Reset Sequences