EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 241

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–16. Number of DQS/DQ Groups per Bank in EP4SE530 Devices in the 1760-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
February 2011 Altera Corporation
(2), (3),
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
(4)
I/O Bank 1B
24 User I/Os
42 User I/Os
I/O Bank 2B
I/O Bank 1C
I/O Bank 2C
24 User I/Os
I/O Bank 1A
42 User I/Os
I/O Bank 2A
7–16:
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=2
x8/x9=2
x8/x9=3
x8/x9=3
x8/x9=3
x4=4
x4=6
DLL1
x4=4
x4=6
DLL0
x4=7
x4=7
I/O Bank 8A
I/O Bank 3A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 3C
I/O Bank 8C
32 User I/Os
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=1
in the 1760-Pin FineLine BGA
x8/x9=1
x4=3
x4=3
EP4SE530 Devices
UP
and R
DN
I/O Bank 7C
32 User I/Os
I/O Bank 4C
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=1
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=3
x4=3
I/O Bank 7B
I/O Bank 4B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 7A
I/O Bank 4A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
Stratix IV Device Handbook Volume 1
and R
DN
pins for OCT calibration, you
I/O Bank 6C
42 User I/Os
42 User I/Os
I/O Bank 5C
24 User I/Os
x16/x18=1
x32/x36=0
I/O Bank 5A
50 User I/Os
I/O Bank 6B
24 User I/Os
I/O Bank 5B
I/O Bank 6A
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=2
x8/x9=3
x8/x9=2
x8/x9=3
x4=6
x4=6
x4=4
x4=7
DLL2
x4=4
DLL3
x4=7
(Note
7–21
1),