EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1012

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–54
Table 1–17. MegaWizard Plug-In Manager Options (PCIe 2 Screen) (Part 2 of 2)
Stratix IV Device Handbook Volume 3
Create a pipeelecidle output port
for Electrical Idle detect status
signal.
Create a pipephydonestatus
output port to indicate PIPE
completed power state transitions.
Create a pipe8b10binvpolarity
port to enable polarity inversion in
PIPE.
Create a powerdn input port for
PIPE powerdown directive.
ALTGX Setting
Enabling this option creates the pipeelecidle
output status port that is forwarded to the FPGA
fabric.
■
■
The pipeelecidle signal is asynchronous to the
receiver data path.
This is an output status signal forwarded to the
FPGA fabric. The completion of various PHY
functions; for example, receiver detection, power
state transition, clock switch, and rate switch, are
indicated on this pipephydonestatus signal by
driving this signal high for one parallel clock cycle.
This optional port allows you to dynamically reverse
every bit of the received data at the input of the
8B/10B decoder.
Enabling this option creates an input control port
powerdn[1:0] for each transceiver channel.
If you select Enable Electrical Idle Inference
Module, the pipeelecidle signal is driven high
when the electrical idle inference module infers
an electrical idle condition depending on the logic
driven on the rx_elecidleinfersel[2:0]
port. Otherwise, it is driven low.
If you do not select Enable Electrical Idle
Inference Module, the rx_signaldetect
output signal from the signal threshold detection
circuitry is inverted and driven on the
pipeelecidle port.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Electrical Idle Inference”
section in the
Architecture in Stratix IV
Devices
“PCIe Mode” section in the
Transceiver Architecture in
Stratix IV Devices
“PCIe Mode” section in the
Transceiver Architecture in
Stratix IV Devices
“Power State Management”
section and Table 1-51 in the
Transceiver Architecture in
Stratix IV Devices
February 2011 Altera Corporation
chapter.
Reference
Transceiver
Protocol Settings
chapter.
chapter.
chapter.