EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 414

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

11–8
Table 11–4. Error Detection Registers (Part 2 of 2)
Error Detection Timing
Table 11–5. Minimum and Maximum Error Detection Frequencies
Stratix IV Device Handbook Volume 1
JTAG Update Register
User Update Register
JTAG Shift Register
User Shift Register
JTAG Fault Injection
Register
Fault Injection Register
Device Type
Stratix IV
Register
Error Detection
100 MHz / 2
When you enable the CRC feature through the Quartus II software, the device
automatically activates the CRC process after entering user mode, after configuration,
and after initialization is complete.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the error
location search, after the error message register is updated. At the end of this cycle,
the CRC_ERROR pin is pulled low for a minimum of 32 clock cycles. If the next frame
contains an error, CRC_ERROR is driven high again after the error message register is
overwritten by the new value. You can start to unload the error message on each
rising edge of the CRC_ERROR pin. Error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
detection frequencies based on the best performance of the internal configuration
oscillator.
Frequency
This register is automatically updated with the contents of the error message register one cycle
after the 46-bit register content is validated. It includes a clock enable that must be asserted prior
to being sampled into the JTAG shift register. This requirement ensures that the JTAG update
register is not being written into by the contents of the error message register at the same time
that the JTAG shift register is reading its contents.
This register is automatically updated with the contents of the Error Message Register, one cycle
after the 46-bit register content is validated. It includes a clock enable that must be asserted prior
to being sampled into the User Shift Register. This requirement ensures that the User Update
Register is not being written into by the contents of the Error Message Register at exactly the
same time that the User Shift Register is reading its contents.
This register is accessible by the JTAG interface and allows the contents of the JTAG Update
Register to be sampled and read by the JTAG instruction SHIFT_EDERROR_REG.
This register is accessible by the core logic and allows the contents of the User Update Register to
be sampled and read by user logic.
This 21-bit register is fully controlled by the JTAG instruction EDERROR_INJECT. This register
holds the information of the error injection that you want in the bitstream.
The content of the JTAG Fault Injection Register is loaded into this 21-bit register when it is being
updated.
n
Detection Frequency
Maximum Error
50 MHz
Table 11–5
Description
Minimum Error Detection
lists the minimum and maximum error
Frequency
390 kHz
Chapter 11: SEU Mitigation in Stratix IV Devices
February 2011 Altera Corporation
1, 2, 3, 4, 5, 6, 7, 8
Valid Divisors (n)
Error Detection Timing