EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1152

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–2
Document Revision History
Table 2–1. Document Revision History
Stratix IV Device Handbook Volume 4
February 2011
September 2010
April 2010
March 2010
February 2010
November 2009
Date
Version
Table 2–5
1.0
1.5
1.4
1.3
1.2
1.1
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Removed the
Feedback Equalization in Stratix IV Devices
Moved the
Stratix IV Devices
Moved the
the
Minor text edits.
Added corrections for the Adaptive Equalization (AEQ) section of the Stratix IV Dynamic
Reconfiguration chapter.
Added new information for the Decision Feedback Equalization (DFE) feature.
Added corrections for the “Power-On Reset Circuitry” and “Power-On Reset
Specifications” sections to of the Hot Socketing and Power-On Reset in Stratix IV Devices
chapter.
Moved the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correct
Power-Up Sequence for Production Devices”, and “Correct Power-Up Sequence for
Production Devices” sections to the Hot Socketing and Power-On Reset in Stratix IV
Devices chapter.
Moved the “Power-On Reset Circuit” and “JTAG TMS and TDI Pin Pull-Up Resistor Value
Specification” sections to the Configuration, Design Security, Remote System Upgrades
with Stratix IV Devices chapter.
Moved the “Summary of OCT Assignments” section to the I/O Features in Stratix IV
Devices chapter.
Added the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correction to
POR Signal Pulse Width Delay Times”, “Correct Power-Up Sequence for Production
Devices”, “Power-On Reset Circuit”, “Summary of OCT Assignments”, and “JTAG TMS
and TDI Pin Pull-Up Resistor Value Specification” sections.
Minor text edits.
Stratix IV GX enhanced transceiver data rate specifications in
Initial release.
lists the revision history for this chapter.
Hot Socketing and Power-On Reset in Stratix IV Devices
“Adaptive Equalization (AEQ)”
“Power-On Reset Circuitry”
“Decision Feedback Equalization (DFE)”
chapter.
Changes
and
Chapter 2: Addendum to the Stratix IV Device Handbook
sections to the
is published.
“Power-On Reset Specifications”
section now that
Dynamic Reconfiguration in
chapter.
February 2011 Altera Corporation
– 4 commercial speed grade.
Document Revision History
AN 612: Decision
sections to