EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 335

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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SIV51010-3.3
Overview
Stratix IV Device Handbook Volume 1
April 2011
April 2011
SIV51010-3.3
This chapter describes the configuration, design security, and remote system
upgrades in Stratix
Stratix IV devices provide configuration data decompression. They also provide a
built-in design security feature that protects your designs against IP theft and
tampering of your configuration files.
Stratix IV devices also offer remote system upgrade capability so that you can
upgrade your system in real-time through any network. This helps to deliver feature
enhancements and bug fixes and provides error detection, recovery, and status
information to ensure reliable reconfiguration.
This chapter describes supported configuration schemes for Stratix IV devices,
instructions about how to execute the required configuration schemes, and the
necessary pin settings.
Stratix IV devices use SRAM cells to store configuration data. As SRAM is volatile,
you must download configuration data to the Stratix IV device each time the device
powers up. You can configure Stratix IV devices using one of four configuration
schemes:
■
■
■
■
All configuration schemes use either an external controller (for example, a MAX
device or microprocessor), a configuration device, or a download cable. For more
information, refer to
This chapter includes the following sections:
■
■
■
■
■
■
■
■
■
Fast passive parallel (FPP)
Fast active serial (AS)
Passive serial (PS)
Joint Test Action Group (JTAG)
“Configuration Schemes” on page 10–2
“Configuration Features” on page 10–4
“Fast Passive Parallel Configuration” on page 10–6
“Fast Active Serial Configuration (Serial Configuration Devices)” on page 10–16
“Passive Serial Configuration” on page 10–24
“JTAG Configuration” on page 10–34
“Device Configuration Pins” on page 10–39
“Configuration Data Decompression” on page 10–47
“Remote System Upgrades” on page 10–49
®
IV devices. To save configuration memory space and time,
“Configuration Features” on page
10. Configuration, Design Security, and
Remote System Upgrades in Stratix IV
10–4.
Devices
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®
II