EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 591

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–55. Transceiver Clock Frequencies Signaling Rates in PCIe ×4 Mode (Part 2 of 2)
Figure 1–117. Low-Speed Parallel Clock Switching in PCIe ×4 Mode
February 2011 Altera Corporation
Parallel Recovered Clock
FPGA Fabric-Transceiver Interface
Clock
Low-Speed Parallel Clock
pipephydonestatus[0]
pipephydonestatus[3]
Transceiver Clocks
1
rateswitch
The PCIe clock switch circuitry in the CMU0 clock divider block performs the clock
switch between 250 MHz and 500 MHz on the low-speed parallel clock when
switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates. It indicates
successful completion of clock switch on the pcie_gen2switchdone signal to the PCIe
rateswitch controller. The PCIe rateswitch controller forwards the clock switch
completion status to the PCIe interface block. The PCIe interface block communicates
the clock switch completion status to the PHY-MAC layer by asserting the
pipephydonestatus signal of all bonded channels for one parallel clock cycle.
Figure 1–117
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch signal.
The rateswitch completion is shown marked with a one clock cycle assertion of the
pipephydonestatus signal of all bonded channels.
Time T1 from a transition on the rateswitch signal to the assertion of
pipephydonestatus is pending characterization.
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the FPGA fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The FPGA fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO of
all bonded channels, respectively. It is also routed to the FPGA fabric on a global or
regional clock resource and looped back to clock the write port and read port of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. Due to the routing delay between the write and read clock of the
transmitter and receiver phase compensation FIFOs, the write pointers and read
pointers might collide during a rateswitch between 125 MHz and 250 MHz. To avoid
250 MHz (Gen1)
Gen1 (2.5 Gbps) to Gen2 (5 Gbps) Switch
shows the low-speed parallel clock switch between Gen1 (250 MHz) and
(Low-to-High Transition on the
T1
250 MHz to 500 MHz
125 MHz to 250 MHz
rateswitch Signal)
500 MHz (Gen2)
Stratix IV Device Handbook Volume 2: Transceivers
Gen2 (5 Gbps) to Gen1 (2.5 Gbps) Switch
(High-to-Low Transition on the
T1
500 MHz to 250 MHz
250 MHz to 125 MHz
rateswitch Signal)
250 MHz (Gen1)
1–147