EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 640

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–196
Stratix IV Device Handbook Volume 2: Transceivers
10G ATX PLL Block
Each Stratix IV GT device has two 10G ATX PLL blocks, one located on each side of
the device. The 10G ATX PLLs provide low-jitter transceiver clocks to implement
40G/100G Ethernet and SFI-S links specified by IEEE802.3ba and OIF specifications.
In EP4S40G2F40 and EP4S40G5H40 devices, you can use each 10G ATX PLL to
generate transceiver clocks for up to six channels at data rates of up to 11.3 Gbps each.
In EP4S100G2F40, EP4S100G5H40, and EP4S100G5F45 devices, you can use each 10G
ATX PLL to generate transceiver clocks for up to 12 channels at data rates of up to
11.3 Gbps each.
Figure 1–163
to 11.3 Gbps in each Stratix IV GT device.
The 10G ATX PLL block consists of:
■
■
The 10G ATX PLL architecture is functionally similar to the 6G ATX PLL architecture,
except that it is optimized for the 10 Gbps data rate range.
Figure 1–160
device families.
Figure 1–160. Location of ATX PLL Blocks in a Four-Transceiver Block Stratix IV GX Device (Two
on Each Side)
10G ATX PLL—Synthesizes the input reference clock to generate the high-speed
serial transceiver clock at frequency of half the configured data rate
ATX clock divider block—Divides the high-speed serial clock from the 10G ATX
PLL to generate the low-speed parallel transceiver clock
and
shows the location of the ATX PLL blocks in two transceiver block
Figure 1–164
ATX PLL L0 (6G)
GXBL0
GXBL1
show transceiver channels that support data rates up
Chapter 1: Transceiver Architecture in Stratix IV Devices
ATX PLL R0 (6G)
GXBR0
GXBR1
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation